FIG. 19 is a diagram illustrating a prior art field effect transistor (referred to as an FET), having a SAG (self aligned gate) structure in which a gate electrode is offset toward the source. The FET includes a GaAs substrate 1j, an i-type GaAs layer 100 on the GaAs substrate 1j, a p type GaAs layer 2j on the GaAs substrate 1j, and an n type GaAs layer 74 on the GaAs semiconductor substrate 1j. The n type GaAs layer 74 has an n type GaAs region 3j and an n.sup.+ type GaAs region 7j. The donor concentration of the n type GaAs region 3j is about 2.times.10.sup.17 /cm.sup.3, and the donor concentration of the n.sup.+ type GaAs region 7j is about 1.times.10.sup.18 /cm.sup.3. The FET includes a gate electrode 4 comprising a refractory metal, for example, WSi, on the n type GaAs region 3j. The gate length of the gate electrode 4 is normally 0.5-1.0 .mu.m. A drain electrode 8 is located on the drain side n.sup.+ type GaAs region 7j and a source electrode 9 is located on the source side n.sup.+ type GaAs region 7j. The drain electrode 8 and the source electrode 9 are an Ni layer 20 nanometers (nm) thick on an AuGe layer 50 nm thick and an Au layer 250 nm thick on the Ni layer.
A description is given of a prior art method of fabricating the FET as shown in the cross-sectional views of FIGS. 20(a)-20(e). First, ions of Mg are implanted into the GaAs substrate with an accelerating voltage of 150 keV and a dosage of 3.times.10.sup.12 /cm.sup.2, and an upper layer portion of the GaAs semiconductor substrate is changed to p type GaAs, thereby forming a p type GaAs layer. Next, Si ions are implanted into the p type GaAs layer at 70 kev and a dosage of 7.times.10.sup.12 /cm.sup.2, changing the upper layer portion of the p type GaAs layer to n type GaAs, and forming an n type GaAs layer. After the successive Mg and Si implantations, the semiconductor substrate is annealed to activate the implanted layers. Thus, the n type GaAs layer 31j and the p type GaAs layer 20j on the GaAs layer 100 shown in FIG. 20(a) are formed.
Thereafter, on the entire surface of the n type GaAs layer 31j, a refractory metal film comprising WSi 400 nm thick is deposited by sputtering. Next, patterning of resist for forming a gate electrode is carried out and isotropic etching using the resist as a mask is performed by RIE or ECR, thereby forming the gate electrode 4 shown in FIG. 20(a).
After forming the gate electrode 4, in the step of FIG. 20(b), an insulating film 5 is formed by plasma CVD on the n type GaAs layer 31j and the gate electrode 4. The thickness t of the film 5 is 0.4 .mu.m.
After forming the insulating film 5, in the step of FIG. 20(c), isotropic ECR etching is carried out, leaving portions of the insulating film 5 at the side wall of the gate electrode 4 and forming the side wall 51. While etching the insulating film 5, the etching selectivity ratio between the n type GaAs layer 31j and the insulating film 5 cannot be made large, resulting in removing a portion of the surface of the n type GaAs layer 31j together with the insulating film 5. Thereby, an n type GaAs layer 30j having an etched portion 80 is formed. The depth of the etched portion 80 is generally about 50 nm. In addition, the width L.sub.SW of the sidewall has a relation with the thickness t of the insulating film 5 shown in FIG. 20(b), EQU L.sub.SW =2/3.multidot.t.
The width L.sub.SW of this sidewall 51 influences the transistor characteristics and it is possible to control the sidewall width L.sub.SW by controlling the thickness t, thereby adjusting the transistor characteristics. In this example, since the thickness t is 0.4 .mu.m, L.sub.SW is about 0.27 .mu.m.
After forming the sidewall 51, photoresist 6 is formed with an offset at the side of the drain electrode 8 that is formed later as shown in FIG. 20(d). The resist 6 has an offset of 1 .mu.m from the end of the gate electrode 4. Using the gate electrode 4, the sidewall 51, and the photoresist 6 as a mask, Si ions are implanted into the GaAs semiconductor substrate at 100 keV and a dosage of 3.times.10.sup.13 /cm.sup.2. Thereby, the n type GaAs region 3j and the n.sup.+ GaAs region 70j are formed, and, as shown in FIG. 20(d), an n type GaAs layer 32j, including the n type GaAs region 3j and the n.sup.+ type GaAs region 70j, is formed on the p type GaAs layer 2j that is produced by changing the p type GaAs layer 20j.
The sidewall 51 and the photoresist 6 are removed and the n.sup.+ type GaAs region 70j is activated by annealing, thereby forming an n.sup.+ type GaAs region 7j shown in FIG. 20(e). As a result, a GaAs semiconductor substrate 1j including the n type GaAs layer 74 comprising the p type GaAs layer 2j, n type GaAs region 3j, and the n.sup.+ type GaAs region 7j is formed on the GaAs layer 100. As shown in FIG. 20(e), a drain electrode 8 and a source electrode 9 are formed by evaporation and liftoff, completing the FET.
The SAGFET having such a structure is mainly used for outputting high power. The DC characteristics of importance for a high power FET include drain breakdown voltage and gate-to-drain breakdown voltage (V.sub.gdo). In order to increase these breakdown voltages, high dopant concentration regions are located at respective portions spaced from the gate electrode by using the sidewall 51 and the resist 6 as a mask. The interval between the gate electrode 4 and the drain electrode 8 is larger than the interval between the gate electrode 4 and the source electrode 9, producing an offset structure. The drain breakdown voltage and the gate-drain voltage (V.sub.gdo) are increased by increasing the distance between the gate electrode 4 and the drain electrode 8, thereby realizing a high breakdown voltage.
A description is given of the operation of the prior art FET with reference to FIG. 21 showing an enlarged cross-section in the vicinity of the gate electrode 4. When a negative voltage is applied to the gate electrode 4 in order to control the drain current, a gate depletion layer is generated in the n type GaAs region 3j beneath the gate electrode 4 in accordance with the magnitude of the voltage. For example, when a negative voltage 90a is applied to the gate electrode 4, a gate depletion layer as shown by the line 90 in FIG. 21 is formed. The thickness of the channel beneath the gate electrode 4 is narrowed by the depth of the gate depletion layer, and the drain current I.sub.D flowing toward the source electrode 9 can be controlled in accordance with the applied voltage by controlling the thickness of the channel.
The line 91 in FIG. 21 represents a gate depletion layer that is generated when a negative voltage 91a closer to 0 V than the negative voltage 90a is applied to the gate electrode 4, and the line 92 represents a gate depletion layer that is generated when a negative voltage 92a closer to 0 V than the negative voltage 91a is applied to the gate electrode 4. Further, the line 93 represents the surface depletion layer of the GaAs semiconductor substrate 1j.
FIG. 23 is a cross-sectional view of a prior art semiconductor switching element with a high breakdown voltage. The switching element includes a semiconductor substrate 100 comprising GaAs, an n type semiconductor layer 30r formed on the semiconductor substrate 100 by molecular beam epitaxy (MBE) or ion implantation, a recess 3r formed by engraving the n type semiconductor layer 30r, a gate electrode 40 located in the recess 3r, a drain electrode 8, and a source electrode 9.
The switching element is mainly used as a high power switch. When switching between transmission and reception, the switching element must sufficiently turn off the transmission output. Particularly when a signal of high output is dealt with, it is required that the gate-to-source breakdown voltage (V.sub.gso) and the gate-to-drain breakdown voltage (V.sub.gdo) be quite high. Generally, a high breakdown voltage switching element can achieve a high gate-to-source breakdown voltage (V.sub.gso) and a high gate-to-drain breakdown voltage (V.sub.gdo) by adopting the recess structure as shown in FIG. 23.
The prior art FET semiconductor device is fabricated as described above, and when the sidewalls 51 are formed, the surface of the n type GaAs layer 31j is engraved as shown in FIG. 20(c). However, there is a problem in the transconductance (g.sub.m) of the FET. When the voltage applied to the gate electrode 4 is closer to 0 V than the negative voltage 91a, relative to the thickness of the channel which is narrowed by the gate depletion layer as shown by the line 92 in FIG. 21, the channel narrowed by the surface depletion layer below the engraved part 80 becomes thinner. Therefore, in the prior art FET, if the voltage applied to the gate electrode 4 is closer to 0 V than the negative voltage 91a, channel confinement arises due to the surface depletion layer beneath the engraved part 80. As a result, as shown in FIG. 22(a), the transconductance of the prior art FET is significantly reduced when the gate voltage is reduced from the negative voltage 91a toward the 0 V direction, and a good value is not obtained in the vicinity of 0 V. In other words, in the prior art FET, even when the gate voltage is made closer to 0 V at equal intervals from the minus side to 0 V, the drain current I.sub.D does not increase at equal intervals, as shown in FIG. 22(b).
In addition, when a further increase of the breakdown voltage is required and the voltage applied to the gate electrode is increased, a leakage current from the gate electrode to the high concentration layer is likely to flow.
In the prior art switching element using a recess structure as shown in FIG. 23, the breakdown voltage is controlled by the engraving depth of the n type semiconductor layer 30r. Broadening of the recess 3r in the transverse direction increases the breakdown voltage. However, variations among respective elements in a wafer surface upon forming the recess and variations in lots of wafers are large, so the yield is low. In addition, it is difficult to fabricate such a high breakdown switching element as a planar element. When a high breakdown voltage and monolithic microwave integrated circuit (MMIC) that includes such a switching element and an element including the FET element are fabricated, the fundamental structural difference between planar type devices and recess type devices makes the fabrication process difficult and no improvement in yield is achieved.